Higher circuit density and lower power-delay product have been the impetus for recent developments in semiconductor technology. An exemplary feature of today's advanced semiconductor devices is a self-aligned polysilicon contact as described in U.S. Pat. Nos. 4,453,306 and 4,691,219. In particular, electrical contacts to active elements are made by employing highly doped polycrystalline silicon as conductive contact layers. Self-aligned polysilicon contacts have significantly improved the performance of high speed semiconductor devices by reducing the parasitic capacitances. However, prior art self-aligned contact processes have not been completely satisfactory in effectively reducing the parasitic capacitances when the dimensions of the devices are further reduced. Consequently, the operating speeds of prior art devices have been inversely dependent on the dimensions of the devices. Moreover, these devices are generally characterized by overlapping double polysilicon layers, which limits their compatibility with MOS devices due to the resulting nonplanarity.
It is therefore an object of this invention to provide a new self-aligned contact process for semiconductor devices, which is not only effective in lowering the parasitic capacitances, but also is compatible with any dimensional scaling. It is further an object of this invention to achieve surface planarity by eliminating the need for the polysilicon layers to overlap.